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| EP9312 Data Sheet FEATURES * 200 MHz ARM920T Processor * 16 Kbyte Instruction Cache * 16 Kbyte Data Cache * * * Linux(R), Microsoft(R) Windows(R) CE enabled MMU 100 MHz System Bus Universal Platform Systemon-Chip Processor * * * Accelerator Touchscreen Interface with ADC 8 x 8 Keypad Scanner One Serial Peripheral Interface (SPI) Port MaverickCrunchTM Math Engine * Floating point, integer and signal processing instructions * Optimized for digital music compression and decompression algorithms * Hardware interlocks allow in-line coding MaverickKeyTM IDs 32-bit unique ID can be used for DRM compliance 128-bit random ID Integrated Peripheral Interfaces * 32-bit SDRAM Interface up to 4 banks * 32/16-bit SRAM / FLASH / ROM * Serial EEPROM Interface * EIDE (up to 2 devices) * 1/10/100 Mbps Ethernet MAC * Three UARTs * Three-port USB 2.0 Full Speed Host (OHCI) (12 Mbits per second) * IrDA Interface * LCD and Raster Interface with Graphics * * * * * * 6-channel or 2-channel Serial Audio Interface (I2S) * 2-channel low-cost Serial Audio Interface (AC'97) * 2 High Resolution PWM (16 bits each) Internal Peripherals * 12 Direct Memory Access (DMA) Channels * Real-time Clock with software Trim * Dual PLL controls all clock domains * Watchdog Timer * Two general purpose 16-bit timers * One general purpose 32-bit timer * One 40-bit Debug Timer * Interrupt Controller * Boot ROM Package * 352 pin PBGA COMMUNICATIONS PORTS Serial Audio Interface Peripheral Bus Clocks & Timers USER INTERFACE 12 DMA w/ CHANNEL CRC DMA (3) UARTs w/ IrDA MaverickCrunchTM ARM920T Interrupts & GPIO MaverickKeyTM MaverickLockTM D-Cache 16KB I-Cache 16KB Bus Bridge (3) USB Hosts Boot ROM MMU Keypad & Touch Screen I/F Processor Bus Ethernet MAC EIDE I/F SRAM & Flash I/F Unified SDRAM I/F Video/LCD Controller MEMORY AND STORAGE (c)Copyright 2004 Cirrus Logic (All Rights Reserved) http://www.cirrus.com JUL `04 DS515PP6 1 EP9312 Universal Platform SOC Processor OVERVIEW The EP9312 is an ARM920T-based system-on-a-chip design with a large peripheral set targeted to a variety of applications: * * * * * * * Thin client computers for business and home Internet radio Internet access devices Industrial computers Specialized terminals Point of sale terminals Test and measurement equipment solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. A high-performance 1/10/100 Mbps Ethernet Media Access Controller (EMAC) is included along with external interfaces to SPI, I2S audio, Raster/LCD, IDE storage peripherals, keypad, and touchscreen. A three-port USB 2.0 Full Speed Host (OHCI) (12 Mbits per second) and three UARTs are included as well. The EP9312 is a high-performance, low-power RISCbased single-chip computer built around an ARM920T microprocessor core with a maximum operating clock rate of 200 MHz (184 MHz for industrial conditions). The ARM core operates from a 1.8 V supply, while the I/O operates at 3.3 V with power usage between 100 mW and 750 mW (dependent on speed). The EP9312 is the first of a series of ARM920T-based devices. Derivative chips will have more focused peripheral The ARM920T microprocessor core with separate 16 Kbyte, 64-way set-associative instruction and data caches is augmented by the MaverickCrunchTM coprocessor enabling high speed floating point calculations. MaverickKeyTM unique hardware programmed IDs are a Table A. Change History Revision 1 2 3 4 5 6 Date March 2001 June 2001 August 2001 May 2003 December 2003 July 2004 Initial Release. Upgrade to revision B silicon. Upgrade to revision C silicon. Upgrade to revision D silicon. Update timing data. Update AC data. Add ADC data. Changes (c) 2 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Table of Contents FEATURES .........................................................................................................1 OVERVIEW .........................................................................................................2 Processor Core - ARM920T ......................................................................................... 6 MaverickCrunchTM Math Engine .................................................................................. 6 MaverickKeyTM Unique ID ............................................................................................ 6 General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH) ........................ 6 IDE Interface ................................................................................................................ 7 Ethernet Media Access Controller (MAC) .................................................................... 7 Serial Interfaces (SPI, I2S and AC '97) ........................................................................ 7 Raster/LCD Interface ................................................................................................... 7 Touch Screen Interface with 12-bit Analog-to-Digital Converter (ADC) ....................... 8 64-Keypad Interface ..................................................................................................... 8 Universal Asynchronous Receiver/Transmitters (UARTs) ............................................ 8 Triple Port USB Host .................................................................................................... 9 Two-Wire Interface With EEPROM Support ................................................................ 9 Real-Time Clock with Software Trim ............................................................................ 9 PLL and Clocking ......................................................................................................... 9 Timers ........................................................................................................................ 10 Interrupt Controller ..................................................................................................... 10 Dual LED Drivers ....................................................................................................... 10 General Purpose Input/Output (GPIO) ....................................................................... 10 Reset and Power Management ................................................................................. 10 Hardware Debug Interface ..........................................................................................11 12-Channel DMA Controller ........................................................................................11 Internal Boot ROM ......................................................................................................11 Electrical Specifications .................................................................................12 Absolute Maximum Ratings ....................................................................................... 12 Recommended Operating Conditions ........................................................................ 12 DC Characteristics ..................................................................................................... 13 Timings .............................................................................................................14 Memory Interface ....................................................................................................... 15 IDE Interface .............................................................................................................. 29 Ethernet MAC Interface ............................................................................................ 43 Audio Interface ........................................................................................................... 45 AC'97 ...................................................................................................................... 49 LCD Interface .......................................................................................................... 50 ADC ........................................................................................................................... 51 JTAG .......................................................................................................................... 52 352 Pin BGA Package Outline .......................................................................53 352-Ball PBGA Diagram .................................................................................. 53 352 Pin BGA Pinout (Bottom View) ........................................................................... 54 Acronyms and Abbreviations ........................................................................61 Units of Measurement .....................................................................................61 ORDERING INFORMATION ............................................................................62 (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 3 EP9312 Universal Platform SOC Processor List of Figures Figure 1. Timing Diagram Drawing Key ................................................................................. 14 Figure 2. SDRAM Load Mode Register Cycle Timing Measurement ..................................... 15 Figure 3. SDRAM Burst Read Cycle Timing Measurement ................................................... 16 Figure 4. SDRAM Burst Write Cycle Timing Measurement ................................................... 17 Figure 5. SDRAM Auto Refresh Cycle Timing Measurement ................................................ 18 Figure 6. Static Memory Single Word Read Cycle Timing Measurement .............................. 19 Figure 7. Static Memory Single Word Write Cycle Timing Measurement .............................. 20 Figure 8. Static Memory Multiple Word Read 8 Bit Cycle Timing Measurement ................... 21 Figure 9. Static Memory Multiple Word Write 8 bit Cycle Timing Measurement .................... 22 Figure 10. Static Memory Multiple Word Read 16 Bit Cycle Timing Measurement ............... 23 Figure 11. Static Memory Multiple Word Write 16 bit Cycle Timing Measurement ................ 24 Figure 12. Static Memory Burst Read Cycle Timing Measurement ....................................... 25 Figure 13. Static Memory Single Read Wait Cycle Timing Measurement ............................. 26 Figure 14. Static Memory Single Write Wait Cycle Timing Measurement .............................. 27 Figure 15. Static Memory Turnaround Cycle Timing Measurement ....................................... 28 Figure 16. Register Transfer to/from Device .......................................................................... 30 Figure 17. PIO Data Transfer to/from Device ......................................................................... 32 Figure 18. Multiword DMA Data Transfer ............................................................................... 33 Figure 19. Initiating an Ultra DMA data-in Burst ..................................................................... 35 Figure 20. Sustained Ultra DMA data-in Burst ....................................................................... 36 Figure 21. Host Pausing an Ultra DMA data-in Burst ............................................................. 36 Figure 22. Device Terminating an Ultra DMA data-in Burst ................................................... 37 Figure 23. Host Terminating an Ultra DMA data-in Burst ....................................................... 38 Figure 24. Initiating an Ultra DMA data-out Burst .................................................................. 39 Figure 25. Sustained Ultra DMA data-out Burst ..................................................................... 40 Figure 26. Device Pausing an Ultra DMA data-out Burst ....................................................... 40 Figure 27. Host Terminating an Ultra DMA data-out Burst .................................................... 41 Figure 28. Device Terminating an Ultra DMA data-out Burst ................................................. 42 Figure 29. Ethernet MAC Timing Measurement ..................................................................... 44 Figure 30. SPI Single Transfer Timing Measurement ............................................................ 46 Figure 31. Microwire Frame Format, Single Transfer ............................................................ 46 Figure 32. SPI Format with SPH=1 Timing Measurement ..................................................... 47 Figure 33. Inter-IC Sound (I2S) Timing Measurement ........................................................... 48 Figure 34. AC `97 Configuration Timing Measurement .......................................................... 49 Figure 35. LCD Timing Measurement .................................................................................... 50 Figure 36. ADC Transfer Function ......................................................................................... 51 Figure 37. JTAG Timing Measurement .................................................................................. 52 Figure 38. 352 Pin PBGA Pin Diagram .................................................................................. 53 Figure 40. 352 PIN BGA PINOUT ................................................................................... 55 (c) 4 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor List of Tables Table A. Change History .......................................................................................................... 2 Table B. General Purpose Memory Interface Pin Assignments .............................................. 6 Table C. IDE Interface Pin Assignments .................................................................................. 7 Table D. Ethernet Media Access Controller Pin Assignments ................................................. 7 Table E. Audio Interfaces Pin Assignment .............................................................................. 7 Table F. LCD Interface Pin Assignments ................................................................................ 8 Table G. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments ... 8 Table H. 64-Key Keypad Interface Pin Assignments ............................................................... 8 Table I. Universal Asynchronous Receiver/Transmitters Pin Assignments ............................ 9 Table J. Triple Port USB Host Pin Assignments ..................................................................... 9 Table K. Two-Wire Port with EEPROM Support Pin Assignments .......................................... 9 Table L. Real-Time Clock with Pin Assignments ..................................................................... 9 Table M.PLL and Clocking Pin Assignments .......................................................................... 9 Table N. Interrupt Controller Pin Assignment ........................................................................ 10 Table O. Dual LED Pin Assignments ..................................................................................... 10 Table P. General Purpose Input/Output Pin Assignment ...................................................... 10 Table Q. Reset and Power Management Pin Assignments ................................................... 10 Table R. Hardware Debug Interface ...................................................................................... 11 Table R. 352 Pin Diagram Dimensions .................................................................................. 54 Table S. Pin Descriptions ..................................................................................................... 58 Table T. Pin Multiplex Usage Information ............................................................................. 60 (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 5 EP9312 Universal Platform SOC Processor Processor Core - ARM920T The ARM920T is a Harvard architecture processor with separate 16 Kbyte instruction and data caches with an 8word line length but a unified memory. The processor utilizes a five-stage pipeline consisting of fetch, decode, execute, memory and write stages. Key features include: * * * * * * * * ARM (32-bit) and Thumb (16-bit compressed) instruction sets 32-bit Advanced Micro-Controller Bus Architecture (AMBA) 16 Kbyte Instruction Cache with lockdown 16 Kbyte Data Cache (programmable write-through or write-back) with lockdown MMU for Linux(R), Microsoft(R) Windows(R) CE and other operating systems Translation Look Aside Buffers with 64 Data and 64 Instruction Entries Programmable Page Sizes of 64 Kbyte, 4 Kbyte, and 1 Kbyte Independent lockdown of TLB Entries provide OEMs with a method of utilizing specific hardware IDs such as those assigned for SDMI (Secure Digital Music Initiative) or any other authentication mechanism. Both a specific 32-bit ID as well as a 128-bit random ID is programmed into the EP9312 through the use of laser probing technology. These IDs can then be used to match secure copyrighted content with the ID of the target device the EP9312 is powering, and then deliver the copyrighted information over a secure connection. In addition, secure transactions can benefit by also matching device IDs to server IDs. MaverickKey IDs provide a level of hardware security required for today's Internet appliances. General Purpose Memory Interface (SDRAM, SRAM, ROM, FLASH) The EP9312 features a unified memory address model where all memory devices are accessed over a common address/data bus. A separate internal port is dedicated to the read-only Raster/LCD refresh engine, while the rest of the memory accesses are performed via the Processor bus. The SRAM memory controller supports 8, 16 and 32-bit devices and accommodates an internal boot ROM concurrently with 32-bit SDRAM memory. * * * * * 1-4 banks of 32-bit 66 or 100 MHz SDRAM One internal port dedicated to the Raster/LCD Refresh Engine (Read Only) One internal port dedicated to the rest of the chip via the Processor bus Address and data bus shared between SDRAM, SRAM, ROM, and FLASH memory Both NAND and NOR FLASH memory supported Table B. General Purpose Memory Interface Pin Assignments MaverickCrunchTM Math Engine The MaverickCrunch Engine is a mixed-mode coprocessor designed primarily to accelerate the math processing required to rapidly encode digital audio formats. It accelerates single and double precision integer and floating point operations plus an integer multiply-accumulate (MAC) instruction that is considerably faster than the ARM920T's native MAC instruction. The ARM920T coprocessor interface is utilized thereby sharing its memory interface and instruction stream. Hardware forwarding and interlock allows the ARM to handle looping and addressing while MaverickCrunch handles computation. Features include: * * * * * * * * IEEE-754 single and double precision floating point 32 / 64-bit integer Add / multiply / compare Integer MAC 32-bit input with 72-bit accumulate Integer Shifts Floating point to/from integer conversion Sixteen 64-bit register files Four 72-bit accumulators Pin Mnemonic SDCLK SDCLKEN SDCSn[3:0] RASn CASn SDWEn CSn[7:6] and CSn[3:0] AD[25:0] DA[31:0] DQMn[3:0] WRn RDn WAITn Pin Description SDRAM Clock SDRAM Clock Enable SDRAM Chip Selects 3-0 SDRAM RAS SDRAM CAS SDRAM Write Enable Chip Selects 7, 6, 3, 2, 1, 0 Address Bus 25-0 Data Bus 31-0 SDRAM Output Enables / Data Masks SRAM Write Strobe SRAM Read / OE Strobe SRAM Wait Input MaverickKeyTM Unique ID MaverickKey unique hardware programmed IDs are a solution to the growing concern over secure web content and commerce. With Internet security playing an important role in the delivery of digital media such as books or music, traditional software methods are quickly becoming unreliable. The MaverickKey unique IDs (c) 6 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor IDE Interface The IDE Interface provides an industry-standard connection to two AT Advanced Packet Interface (ATAPI) compliant devices. The IDE port will attach to a master and a slave device. The internal DMA controller performs all data transfers using the Multiword DMA and Ultra DMA modes. The interface supports the following operating modes: * * * PIO Mode 4 Multiword DMA Mode 2 Ultra DMA Mode 4 Table C. IDE Interface Pin Assignments Serial Interfaces (SPI, I2S and AC '97) The SPI port can be configured as a master or a slave, supporting the National Semiconductor(R), Motorola(R) and Texas Instruments(R) signaling protocols. The AC'97 port supports multiple codecs for multichannel audio output with a single stereo input. Three I2S ports can be configured to support six channel 24 bit audio. These ports are multiplexed so that I2S port 0 will take over either the AC'97 pins or the SPI pins. The second and third I2S ports' serial input and serial output pins are multiplexed with EGPIO[4,5,6,13]. The clocks supplied in the first I2S port are also used for the second and third I2S ports. * * * Normal Mode: One SPI Port and one AC'97 Port I2S on SSP Mode: One AC'97 Port and up to three I2S Ports I2S on AC'97 Mode: One SPI Port and up to three I2S Ports Table E. Audio Interfaces Pin Assignment Pin Mnemonic DD[15-0] IDEDA[2-0] IDECSn[0,1] DIORn DIOWn DMACKn Pin Description IDE Data bus IDE Device address IDE Chip Select 0 and 1 IDE Read Strobe IDE Write Strobe IDE DMA acknowledge ` Ethernet Media Access Controller (MAC) The MAC subsystem is compliant with the ISO/TEC 802.3 topology for a single shared medium with several stations. Multiple MII-compliant PHYs are supported. Features include: * * Supports 1/10/100 Mbps transfer rates for home / small-business / large-business applications Interfaces to an off-chip PHY through industry standard Media Independent Interface (MII) Table D. Ethernet Media Access Controller Pin Assignments Pin Name SCLK1 SFRM1 Normal Mode Pin Description SPI Bit Clock I2S on SSP Mode Pin Description I2S Serial Clock I2S on AC'97 Mode Pin Description SPI Bit Clock SPI Frame Clock SPI Serial Input SPI Serial Output SPI Frame Clock I2S Frame Clock I2S Serial Input I2S Serial Output (No I2S Master Clock) SSPRX1 SPI Serial Input SSPTX1 SPI Serial Output ARSTn AC'97 Reset AC'97 Reset AC'97 Bit Clock AC'97 Frame Clock AC'97 Serial Input AC'97 Serial Output I2S Master Clock I2S Serial Clock I2S Frame Clock I2S Serial Input I2S Serial Output Pin Mnemonic MDC MDIO RXCLK MIIRXD[3:0] RXDVAL RXERR TXCLK MIITXD[3:0] TXEN TXERR CRS CLD Pin Description Management Data Clock Management Data I/O Receive Clock Receive Data Receive Data Valid Receive Data Error Transmit Clock Transmit Data Transmit Enable Transmit Error Carrier Sense Collision Detect ABITCLK AC'97 Bit Clock ASYNC ASDI ASDO AC'97 Frame Clock AC'97 Serial Input AC'97 Serial Output Raster/LCD Interface The Raster/LCD interface provides data and interface signals for a variety of display types. It features fully programmable video interface timing for non-interlaced flat panel or dual scan displays. Resolutions up to 1280 x 1024 are supported from a unified SDRAM based frame buffer. A 16-bit PWM provides control for LCD panel contrast. LCD specific features include: (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 7 EP9312 Universal Platform SOC Processor * * * * * * * * Timing and interface signals for digital LCD and TFT displays Full programmability for either non-interlaced or dualscan color and grayscale flat panel displays Dedicated data path to SDRAM controller for improved system performance Pixel depths of 4, 8, 16, or 18-bits per pixel or 256 levels of grayscale Hardware Cursor up to 64 x 64 pixels 256 x 18 Color Lookup Table Hardware Blinking 8-bit interface to low end panel Table F. LCD Interface Pin Assignments 64-Keypad Interface The keypad circuitry scans an 8 x 8 array of 64 normally open, single pole switches. Any one or two keys depressed will be de-bounced and decoded. An interrupt is generated whenever a stable set of depressed keys is detected. If the keypad is not utilized, the 16 column/row pins may be used as general purpose I/O. The Keypad interface: * * * * * Provides scanning, debounce and decoding for a 64key array. Scans an 8-row by 8-column matrix. May decode 2 keys at once. Generates an interrupt when a new stable key is determined. Also generates a 3-key reset interrupt. Table H. 64-Key Keypad Interface Pin Assignments Pin Mnemonic SPCLK P[17:0] HSYNC / LP VCSYNC / FP BLANK BRIGHT Pixel Clock Pin Description Pixel Data Bus [17:0] Horizontal Synchronization / Line Pulse Vertical or Composite Synchronization / Frame Pulse Composite Blank Pulse Width Modulated Brightness Pin Mnemonic COL[7:0] ROW[7:0] Pin Description Key Matrix Column Inputs Key Matrix Row Inputs Alternative Usage General Purpose I/O General Purpose I/O Touch Screen Interface with 12-bit Analogto-Digital Converter (ADC) The touch screen interface performs all sampling, averaging, ADC range checking, and control for a wide variety of analog resistive touch screens. This controller only interrupts the processor when a meaningful change occurs. The touch screen hardware may be disabled and the switch matrix and ADC controlled directly if desired. Features include: * * * Support for 4, 5, 7, or 8-wire analog resistive touch screens. Flexibility - unused lines may be used for temperature sensing or other functions. Touch screen interrupt function. Table G. Touch Screen Interface with 12-bit Analog-to-Digital Converter Pin Assignments Universal Asynchronous Receiver/Transmitters (UARTs) Three 16550-compatible UARTs are supplied. Two provide asynchronous HDLC (High-level Data Link Control) protocol support for full duplex transmit and receive. The HDLC receiver handles framing, address matching, CRC checking, control-octet transparency, and optionally passes the CRC to the host at the end of the packet. The HDLC transmitter handles framing, CRC generation, and control-octet transparency. The host must assemble the frame in memory before transmission. The HDLC receiver and transmitter use the UART FIFOs to buffer the data streams. A third IrDA(R) compatible UART is also supplied. * UART1 supports modem bit rates up to 115.2 Kbps, supports HDLC and includes a 16 byte FIFO for receive and a 16 byte FIFO for transmit. Interrupts are generated on Rx, Tx and modem status change. UART2 contains an IrDA encoder operating at either the slow (up to 115 Kbps), medium (0.576 or 1.152 Mbps), or fast (4 Mbps) IR data rates. It also has a 16 byte FIFO for receive and a 16 byte FIFO for transmit. UART3 supports HDLC and includes a 16 byte FIFO for receive and a 16 byte FIFO for transmit. Interrupts are generated on Rx and Tx. Pin Mnemonic Xp, Xm Yp, Ym SXp, SXm SYp, SYm Pin Description Touch screen ADC X Axis Touch screen ADC Y Axis Touch screen ADC X Axis Voltage Feedback Touch screen ADC Y Axis Voltage Feedback * * (c) 8 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Table I. Universal Asynchronous Receiver/Transmitters Pin Assignments Table J. Triple Port USB Host Pin Assignments Pin Mnemonic Pin Mnemonic TXD0 RXD0 CTSn DSRn / DCDn DTRn RTSn EGPIO[0] / RI TXD1 / SIROUT RXD1 / SIRIN TXD2 RXD2 EGPIO[3] / TENn Pin Name - Description USB Positive signals USB Negative Signals Pin Name - Description UART1 Transmit UART1 Receive UART1 Clear To Send / Transmit Enable UART1 Data Set Ready / Data Carrier Detect UART1 Data Terminal Ready UART1 Ready To Send UART1 Ring Indicator UART2 Transmit / IrDA Output UART2 Receive / IrDA Input UART3 Transmit UART3 Receive HDLC3 Transmit Enable USBp[2:0] USBm[2:0] Two-Wire Interface With EEPROM Support The two-wire interface provides communication and control for EEPROM devices. The EPROM Controller may download device configuration information upon chip reset. Table K. Two-Wire Port with EEPROM Support Pin Assignments Pin Mnemonic EECLK EEDATA Pin Name - Description EEPROM / Two-Wire Interface Clock EEPROM / Two-Wire Interface Data External Power Switch Control Alternative Usage General Purpose I/O General Purpose I/O General Purpose I/O Triple Port USB Host The USB Open Host Controller Interface (Open HCI) provides full speed serial communications ports at a baud rate of 12 Mbits/sec. Up to 127 USB devices (printer, mouse, camera, keyboard, etc.) and USB hubs can be connected to the USB host in the USB "tieredstart" topology. This includes the following features: * * * Compliance with the USB 2.0 specification Compliance with the Open HCI Rev 1.0 specification Supports both low speed (1.5 Mbps) and full speed (12 Mbps) USB device connections * Root HUB integrated with 3 downstream USB ports * Transceiver buffers integrated, over-current protection on ports * Supports power management * Operates as a master on the bus The Open HCI host controller initializes the master DMA transfer with the AHB bus: * * * * Fetches endpoint descriptors and transfer descriptors Accesses endpoint data from system memory Accesses the HC communication area Writes status and retire transfer descriptor SLA[1:0] Real-Time Clock with Software Trim The software trim feature on the real time clock (RTC) provides software controlled digital compensation of the 32.768 KHz crystal oscillator. This compensation is accurate to 1.24 sec/month. Table L. Real-Time Clock with Pin Assignments Pin Mnemonic RTCXTALI RTCXTALO Pin Name - Description Real-Time Clock Oscillator Input Real-Time Clock Oscillator Output PLL and Clocking The Processor and the Peripheral Clocks operate from a single 14.7456 MHz crystal. The Real Time Clock operates from a 32.768 KHz crystal oscillator. Table M. PLL and Clocking Pin Assignments Pin Mnemonic XTALI XTALO VDD_PLL GND_PLL Pin Name - Description Main Oscillator Input Main Oscillator Output Main Oscillator Power Main Oscillator Ground (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 9 EP9312 Universal Platform SOC Processor Timers The Watchdog Timer insures proper operation by requiring periodic attention to prevent a reset-on-timeout. Two 16-bit timers operate as free running down-counters or as periodic timers for fixed interval interrupts and have a range of 0.03 ms to 4.27 seconds. One 32-bit timer, plus a 6-bit prescale counter, has a range of 0.03 s to 73.3 hours. One 40-bit debug timer, plus 6-bit prescale counter, has a range of 1.0 s to 12.7 days. Table O. Dual LED Pin Assignments Pin Mnemonic GRLED REDLED Pin Name Description Green LED Red LED Alternative Usage General Purpose I/O General Purpose I/O General Purpose Input/Output (GPIO) The 16 EGPIO pins may each be configured individually as an output, an input, or an interrupt input. There are 23 pins that may alternatively be used as input, output, or open-drain pins, but do not support interrupts. These pins are: * Key Matrix ROW[7:0], COL[7:0] * Ethernet MDIO * Both LED Outputs * EEPROM Clock and Data * SLA [1:0] 6 pins may alternatively be used as inputs only: * CTSn, DSRn / DCDn * 4 Interrupt Lines 2 pins may alternatively be used as outputs only: * RTSn * ARSTn Table P. General Purpose Input/Output Pin Assignment Interrupt Controller The interrupt controller allows up to 64 interrupts to generate an Interrupt Request (IRQ) or Fast Interrupt Request (FIQ) signal to the processor core. Thirty-two hardware priority assignments are provided for assisting IRQ vectoring, and two levels are provided for FIQ vectoring. This allows time critical interrupts to be processed in the shortest time possible. Internal interrupts may be programmed as active high or active low level sensitive inputs. External interrupts may be programmed as active high level sensitive, active low level sensitive, rising edge triggered, falling edge triggered, or combined rising/falling edge triggered. * * * * * Supports 64 interrupts from a variety of sources (such as UARTs, GPIO, and key matrix) Routes interrupt sources to either the ARM920T's IRQ or FIQ (Fast IRQ) inputs Four dedicated off-chip interrupt lines operate as level sensitive interrupts Any of the 16 GPIO lines maybe configured to generate interrupts Software supported priority mask for all FIQs and IRQs Table N. Interrupt Controller Pin Assignment Pin Mnemonic EGPIO[15:0] Pin Name - Description Expanded General Purpose Input / Output Pins with Interrupts Reset and Power Management The chip may be reset through the PRSTn pin or through the open drain common reset pin, RSTOn. Clocks are managed on a peripheral-by-peripheral basis and may be turned off to conserve power. The processor clock is dynamically adjustable from 0 to 200 MHz (184 MHz for industrial conditions). Table Q. Reset and Power Management Pin Assignments Pin Mnemonic INT[3:0] Pin Name - Description External Interrupt 3-0 Dual LED Drivers Two pins are assigned specifically to drive external LEDs. Pin Mnemonic PRSTn RSTOn Pin Name - Description Power On Reset User Reset In/Out - Open Drain - Preserves Real Time Clock value (c) 10 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Hardware Debug Interface The JTAG interface allows use of ARM's Multi-ICE or other in-circuit emulators. Table R. Hardware Debug Interface 12-Channel DMA Controller The DMA module contains 12 separate DMA channels. Ten of these may be used for peripheral-to-memory or memory-to-peripheral access. Two of these are dedicated to memory-to-memory transfers. Each DMA channel is connected to the 16-bit DMA request bus. The request bus is a collection of requests, Serial Audio and UARTs. Each DMA channel can be used independently or dedicated to any request signal. For each DMA channel, source and destination addressing can be independently programmed to increment, decrement, or stay at the same value. All DMA addresses are physical, not virtual addresses. Pin Mnemonic TCK TDI TDO TMS TRSTn Pin Name - Description JTAG Clock JTAG Data In JTAG Data Out JTAG Test Mode Select JTAG Port Reset Internal Boot ROM The Internal 16 Kbyte ROM allows booting from FLASH memory, SPI or UART. (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 11 EP9312 Universal Platform SOC Processor Electrical Specifications Absolute Maximum Ratings (All grounds = 0 V, all voltages with respect to 0 V) Parameter Symbol RVDD CVDD VDD_PLL VDD_ADC (Note 1) Min - Max 3.96 2.16 2.16 3.96 2 10 50 RVDD+0.3 +125 Unit V V V V W mA mA V C Power Supplies Total Power Dissipation Input Current per Pin, DC (Except supply pins) Output current per pin, DC Digital Input voltage Storage temperature (Note 2) -0.3 -40 Note: 1. Includes all power generated by AC and/or DC output loading. 2. The power supply pins are at recommended maximum values. 3. At ambient temperatures above 70 C, total power dissipation must be limited to less than 2.5 Watts. WARNING: Operation beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Recommended Operating Conditions (All grounds = 0 V, all voltages with respect to 0 V) Parameter Symbol RVDD CVDD VDD_PLL VDD_ADC TA TA FCLK FCLK HCLK HCLK Min 3.0 1.65 1.65 3.0 0 -40 - Typ 3.3 1.80 1.80 3.3 +25 +25 - Max 3.6 1.94 1.94 3.6 +70 +85 200 184 100 92 Unit V V V V C C MHz MHz MHz MHz Power Supplies Operating Ambient Temperature - Commercial Operating Ambient Temperature - Industrial Processor Clock Speed - Commercial Processor Clock Speed - Industrial System Clock Speed - Commercial System Clock Speed - Industrial (c) 12 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor DC Characteristics (TA = 0 to 70 C; CVDD = VDD_PLL = 1.8; RVDD = 3.3 V; All grounds = 0 V; all voltages with respect to 0 V unless otherwise noted) Parameter High level output voltage Low level output voltage High level input voltage Low level input voltage High level leakage current Low level leakage current Vin = 3.3 V Vin = 0 Iout = -4 mA Iout = 4 mA (Note 5) (Note 5) (Note 5) (Note 5) (Note 4) Symbol Voh Vol Vih Vil Iih Iil Min 0.85 x RVDD 0.65 x RVDD -0.3 - Max 0.15 x RVDD VDD + 0.3 0.35 x RVDD 10 -10 Unit V V V V A A Parameter Power Supply Pins (Outputs Unloaded) Power Supply Current: Low-Power Mode Supply Current CVDD / VDD_PLL Total RVDD CVDD / VDD_PLL Total RVDD Min Typ Max Unit - 200 20 2.5 1.0 - mA mA mA mA Note: 4. For open drain pins, high level output voltage is dependent on the external load. 5. All inputs that do not include internal pull-ups or pull-downs, must be externally driven for proper operation (See Table S on page 58). If an input is not driven, it should be tied to power or ground, depending on the particular function. If an I/O pin is not driven and programmed as an input, it should be tied to power or ground through its own resistor. (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 13 EP9312 Universal Platform SOC Processor Timings Timing Diagram Conventions This data sheet contains one or more timing diagrams. The following key explains the components used in these diagrams. Any variations are clearly labelled when they occur. Therefore, no additional meaning should be attached unless specifically stated. Clock High to Low High/Low to High Bus Change Bus Valid Undefined/Invalid Valid Bus to High Impedance State Bus/Signal Omission Figure 1. Timing Diagram Drawing Key Timing Conditions Unless specified otherwise, the following conditions are true for all timing measurements. * TA = 0 to 70 C * CVDD = VDD_PLL = 1.8V * RVDD = 3.3 V * All grounds = 0 V * Logic 0 = 0 V, Logic 1 = 3.3 V * Output loading = 50 pF * Timing reference levels = 1.5 V * The Processor Bus Clock (HCLK) is programmable and is set by the user. The frequency is typically between 33 MHz and 100 MHz (92 MHz for industrial conditions). (c) 14 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Memory Interface Figure 2 through Figure 5 define the timings associated with all phases of the SDRAM. The following table contains the values for the timings of each of the SDRAM modes. Parameter SDCLK high time SDCLK low time SDCLK rise/fall time Signal delay from SDCLK rising edge time Signal hold from SDCLK rising edge time DQMn delay from SDCLK rising edge time DQMn hold from SDCLK rising edge time DA valid setup to SDCLK rising edge time DA valid hold from SDCLK rising edge time Symbol tclk_high tclk_low tclkrf td th tDQd tDQh tDAs tDAh Min - Typ (tHCLK) / 2 (tHCLK) / 2 3 8 4 6 6 2 2 Max - Unit ns ns ns ns ns ns ns ns ns SDRAM Load Mode Register Cycle tclk_low tclk_high tclkrf SDCLK td SDCSn th RASn CASn SDWEn DQMn AD OP-Code DA Figure 2. SDRAM Load Mode Register Cycle Timing Measurement (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 15 EP9312 Universal Platform SOC Processor SDRAM Burst Read Cycle tclk_low SDCLK tclk_high tclkrf td SDCSn th RASn CASn SDWEn tDQd DQMn tDQh AD td tDAs DA tDAh Figure 3. SDRAM Burst Read Cycle Timing Measurement (c) 16 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor SDRAM Burst Write Cycle tclk_low SDCLK td SDCSn th tclk_high tclkrf th RASn CASn SDWEn DQMn AD DA Figure 4. SDRAM Burst Write Cycle Timing Measurement (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 17 EP9312 Universal Platform SOC Processor SDRAM Auto Refresh Cycle tclk_low SDCLK tclk_high tclkrf td SDCSn 7 b d e th RASn CASn SDWEn Note: Chip select shown as bus to illustrate multiple devices being put into auto refresh in one access Figure 5. SDRAM Auto Refresh Cycle Timing Measurement (c) 18 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Static Memory Single Word Read Cycle Parameter AD setup to RDn assert time AD hold from RDn deassert time RDn assert time CSn assert to RDn assert delay time CSn deassert to RDn deassert delay time CSn assert to DQMn assert delay time CSn deassert to DQMn deassert delay time DA setup to RDn deassert time DA hold from RDn deassert time Symbol tADs tADh tRDpw tRDd tRDh tDQMd tDQMh tDAs tDAh Min 0 Typ 5 tHCLK x 2 tHCLK x (WST1 + 2) 0 0 0 0 tHCLK + 6 0 Max tHCLK x 33 - Unit ns ns ns ns ns ns ns ns ns See "Timing Conditions" on page 14 for definition of HCLK. t ADs AD t AD h CSn W Rn t R Dd1 RDn t D QMd1 t R D pw t D QMd2 h t R Dd2 h DQMn t DAs DA t DAh W AIT Figure 6. Static Memory Single Word Read Cycle Timing Measurement (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 19 EP9312 Universal Platform SOC Processor Static Memory Single Word Write Cycle Parameter AD setup to WRn assert time AD hold from WRn deassert time WRn deassert to CSn deassert time CSn to WRn assert delay time WRn assert time CSn to DQMn assert delay time WRn deassert to DQMn deassert time WRn deassert to DA transition time Symbol tADs tADh tCSh tWRd tWRpw tDQMd tDQMh tDAh Min - Typ tHCLK tHCLK x 3 tHCLK 0 tHCLK x (WST1 + 1) 0 0 tHCLK Max - Unit ns ns ns ns ns ns ns ns tADs AD tCSh tWRd WRn tWRpw tADh CSn RDn DQMn tDQMd tDQMh tDAh DA WAIT Figure 7. Static Memory Single Word Write Cycle Timing Measurement (c) 20 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Static Memory 32-bit Read on 8-bit External Bus Parameter AD setup to RDn assert time RDn assert to Address 1 transition time Address 2 assert time Address 3 assert time AD transition to RDn deassert time AD hold from RDn deassert time RDn assert time CSn assert to RDn assert delay time CSn deassert to RDn deassert delay time CSn assert to DQMn assert delay time CSn deassert to DQMn deassert delay time DA setup to AD transition time DA to RDn setup time AD transition to DA transition hold time RDn deassert to DA transition hold time Symbol tADs tAD1 tAD2 tAD3 tAD4 tADh tRDpwL tRDd tRDh tDQMd tDQMh tDAs1 tDAs2 tDAh1 tDAh2 Min - Typ tHCLK tHCLK x (WST1 + 1) tHCLK x (WST1 + 1) tHCLK x (WST1 + 1) tHCLK x (WST1 + 2) tHCLK x 2 tHCLK x (4 x WST1 + 5) 0 0 0 0 6 tHCLK + 6 0 0 Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns t AD s AD t AD 1 t AD2 t AD 3 t AD 4 t ADh CSn W Rn tR D d RDn t D QMd DQMn t DAh1 DA t DAs1 W AIT t D As 1 t DAs1 t DAs2 t D Ah1 t RD PwL t R Dh t D QMh t DAh1 1 t D Ah2 Figure 8. Static Memory Multiple Word Read 8 Bit Cycle Timing Measurement (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 21 EP9312 Universal Platform SOC Processor Static Memory 32-bit Write on 8-bit External Bus Parameter AD setup to WRn assert time WRn deassert to AD transition time AD hold from WRn deassert time CSn hold from WRn deassert time CSn to WRn assert delay time WRn assert time WRn deassert time CSn to DQMn assert delay time DQMn assert time DQMn deassert time WRn / DQMn deassert to DA transition time Symbol tADs tADd tADh tCSh tWRd tWRpwL tWRpwH tDQMd tDQMpwL tDQMpwH tDAh Min - Typ tHCLK tHCLK tHCLK x 3 tHCLK 0 tHCLK x (WST1 + 1) tHCLK x 2 0 tHCLK x (WST1 + 1) tHCLK x 2 tHCLK Max - Unit ns ns ns ns ns ns ns ns ns ns ns tA D s AD tA D d tA Dd t AD d t AD h C Sn t W Rd WRn t W R p wH RD n tD Q M d DQMn t DQ M pwH tD Q M pw H t DQ M p wH t DQ M pwL tD Q M pw L t DQ M p wL tW R pwH t W R pw H t W R p wL tW R pwL t W R pw L t CS h DA tD Ah W AIT Figure 9. Static Memory Multiple Word Write 8 bit Cycle Timing Measurement tD Ah t DA h tD Ah (c) 22 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Static Memory 32-bit Read on 16-bit External Bus Parameter AD setup to RDn assert time RDn assert to AD transition time AD transition to RDn deassert time AD hold from RDn deassert time RDn assert time CSn to RDn assert delay time CSn to RDn deassert delay time CSn to DQMn assert delay time CSn to DQMn deassert delay time DA to ADsetup time DA to RDn setup time AD transition to DA transition hold time RDn deassert to DA transition hold time Symbol tADs tADd1 tADd2 tADh tRDpwL tRDd tRDh tDQMd tDQMh tDAs1 tDAs2 tDAh1 tDAh2 Min - Typ tHCLK tHCLK x (WST1 + 1) tHCLK x (WST1 + 2) tHCLK x 2 tHCLK x (2 x WST1 + 3) 0 0 0 0 6 tHCLK + 6 0 0 Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns tADs AD tADd1 tADd2 tADh CSn WRn RDn tRDd tRDpwl tDQMd tDQMh tRDh DQMn tDAs1 DA tDAh1 tDAs2 tDAh2 WAIT Figure 10. Static Memory Multiple Word Read 16 Bit Cycle Timing Measurement (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 23 EP9312 Universal Platform SOC Processor Static Memory 32-bit Write on 16-bit External Bus Parameter AD setup to WRn assert time WRn deassert to AD transition time AD hold from WRn deassert time CSn hold from WRn deassert time CSn to WRn assert delay time WRn assert time WRn deassert time CSn to DQMn assert delay time DQMn assert time DQMn deassert time WRn / DQMn deassert to DA transition time WRn / DQMn deassert to DA transition time Symbol tADs tADd tADh tCSh tWRd tWRpwL tWRpwH tDQMd tDQMpwL tDQMpwH tDAh1 tDAh2 Min - Typ tHCLK tHCLK 2 x tHCLK tHCLK 0 tHCLK x (WST1 + 1) tHCLK x 2 0 tHCLK x (WST1 + 1) tHCLK x 2 tHCLK tHCLK Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns tADs AD tADd tADh CSn tWRd WRn tWRpwL tWRpwH tWRpwL tCSh RDn tDQMd DQMn tDQpwL tDQpwH tDAh1 DA tDAh2 tDQpwL WAIT Figure 11. Static Memory Multiple Word Write 16 bit Cycle Timing Measurement (c) 24 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Static Memory Burst Read Cycle Parameter CSn assert to Address 1 transition time Address 2 assert time AD hold from CSn deassert time CSn assert time CSn to RDn assert delay time RDn assert time CSn to DQMn assert delay time DQMn assert time DA to AD setup time DA to CSn setup time AD transition to DA transition hold time CSn deassert to DA transition hold time Symbol tADd1 tADd2 tADh tCSpw tRDd tRDpw tDQMd tDQMpw tDAs1 tDAs2 tDAh1 tDAh2 Min 0 Typ tHCLK x (WST1 + 1) tHCLK x (WST2 + 1) tHCLK x 2 tHCLK x ((WST1 + 1) + 4(WST2 + 1)) 0 tHCLK x ((WST1 + 1) + 4(WST2 + 1)) 4 tHCLK x ((WST1 + 1) + 4(WST2 + 1)) 6 tHCLK + 6 0 0 Max - Unit ns ns ns ns ns ns ns ns ns ns ns ns Note: These characteristics are valid when the Page Mode Enable (Burst Mode) bit is set. See the User's Guide for details. tADd1 AD tADd2 tADd2 tADh CSn tCSpw WRn tRDd RDn tDQMd tRDpw DQMn tDQMpw tDAh1 tDAh1 tDAh1 tDAh2 DA tDAs1 WAIT tDAs1 tDAs1 tDAs2 Figure 12. Static Memory Burst Read Cycle Timing Measurement (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 25 EP9312 Universal Platform SOC Processor Static Memory Single Read Wait Cycle Parameter CSn assert to WAIT time WAIT assert time WAIT to CSn deassert delay time Symbol tWAITd tWAITpw tCSnd Min tHCLK x 2 tHCLK x 3 Typ - Max tHCLK x (WST1-2) tHCLK x 510 tHCLK x 5 Unit ns ns ns AD CSn WRn RDn DQMn DA WAIT tWAITd tWAITpw tCSnd Figure 13. Static Memory Single Read Wait Cycle Timing Measurement (c) 26 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Static Memory Single Write Wait Cycle Parameter WAIT to WRn deassert delay time CSn assert to WAIT time WAIT assert time WAIT to CSn deassert delay time Symbol tWRd tWAITd tWAITpw tCSnd Min tHCLK x 2 tHCLK x 2 tHCLK x 3 Typ - Max tHCLK x 4 tHCLK x (WST1-2) tHCLK x 510 tHCLK x 5 Unit ns ns ns ns AD CSn tW Rd WRn RDn DQMn DA tW AITd WAIT tCSnd tW AITpw Figure 14. Static Memory Single Write Wait Cycle Timing Measurement (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 27 EP9312 Universal Platform SOC Processor Static Memory Turnaround Cycle Parameter CSnX deassert to CSnY assert time Symbol tBTcyc Min - Typ tHCLK x (IDCY+1) Max - Unit ns Note: X and Y represent any two chip select numbers. tBTcyc AD X CSn0 Y CSn1 WRn RDn DQMn DA WAIT Figure 15. Static Memory Turnaround Cycle Timing Measurement (c) 28 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor IDE Interface Register Transfers Parameter Cycle time Address valid to DIORn / DIOWn setup DIORn / DIOWn pulse width 8-bit DIORn / DIOWn recovery time DIOWn data setup DIOWn data hold DIORn data setup DIORn data hold DIORn data high impedance state DIORn / DIOWn to address valid hold Read Data Valid to IORDY active (if IORDY initially low after tA) IORDY Setup time IORDY Pulse Width IORDY assertion to release (max) (max) (min) (min) (min) (min) (min) (min) (min) (min) (max) (min) (min) (Note 3) (Note 2) (Note 1) (Note 1) (Notes 1,4) Symbol t0 t1 t2 t2i t3 t4 t5 t6 t6z t9 tRD tA tB tC Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 (in ns) (in ns) (in ns) (in ns) (in ns) 600 70 290 60 30 50 5 30 20 0 35 1250 5 383 50 290 45 20 35 5 30 15 0 35 1250 5 330 30 290 30 15 20 5 30 10 0 35 1250 5 180 30 80 70 30 10 20 5 30 10 0 35 1250 5 120 25 70 25 20 10 20 5 30 10 0 35 1250 5 Note: 1. t0 is the minimum total cycle time, t2 is the minimum DIORn / DIOWn assertion time, and t2i is the minimum DIORn / DIOWn negation time. A host implementation shall lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation. 2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device. 3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at the tA after the activation of DIORn or DIOWn, then t5 shall be met and tRD is not applicable. If the device is driving IORDY negated at the time tA after the activation of DIORn or DIOWn, then tRD shall be met and t5 is not applicable. 4. ATA / ATAPI standards prior to ATA / ATAPI-5 inadvertently specified an incorrect value for mode 2 time t0 by utilizing the 16-bit PIO value. (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 29 EP9312 Universal Platform SOC Processor ADDR valid (Note 1) t9 t1 DIORn/ DIOWn t0 WRITE DD(7:0) (Note 2) t2 t2i t3 t4 READ DD(7:0) (Note 2) t5 t6 t6z IORDY (Note 3,3-1) tA IORDY (Note 3,3-2) tC tRD IORDY (Note 3,3-3) tB Note: tC 1. Device address consists of signals CS0n, CS1n and DA (2:0) 2. Data consists of DD (7:0) 3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made by the host after tA from the assertion of DIORn or DIOWn. The assertion and negation or IORDY are described in the following three cases: 3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. 3-2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: no wait generated. 3-3 Device negates IORDY before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIORn is asserted, the device shall place read data on DD (7:0) for tRD before asserting IORDY. Figure 16. Register Transfer to/from Device (c) 30 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor PIO Data Transfers Parameter Cycle time Address valid to DIORn / DIOWn setup DIORn / DIOWn 16-bit DIORn / DIOWn recovery time DIOWn data setup DIOWn data hold DIORn data setup DIORn data hold DIORn data high impedance state DIORn / DIOWn to address valid hold Read Data Valid to IORDY active (if IORDY initially low after tA) IORDY Setup time IORDY Pulse Width IORDY assertion to release (max) (max) (min) (min) (min) (min) (min) (min) (min) (min) (max) (min) (min) (Note 3) (Note 2) (Note 1) (Note 1) (Note 1) Symbol t0 t1 t2 t2i t3 t4 t5 t6 t6z t9 tRD tA tB tC Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 (in ns) (in ns) (in ns) (in ns) (in ns) 600 70 165 60 30 50 5 30 20 0 35 1250 5 383 50 125 45 20 35 5 30 15 0 35 1250 5 240 30 100 30 15 20 5 30 10 0 35 1250 5 180 30 80 70 30 10 20 5 30 10 0 35 1250 5 120 25 70 25 20 10 20 5 30 10 0 35 1250 5 Note: 1. t0 is the minimum total cycle time, t2 is the minimum DIORn / DIOWn assertion time, and t2i is the minimum DIORn / DIOWn negation time. A host implementation shall lengthen t2 and/or t2i to ensure that t0 is equal to or greater than the value reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation. 2. This parameter specifies the time from the negation edge of DIORn to the time that the data bus is released by the device. 3. The delay from the activation of DIORn or DIOWn until the state of IORDY is first sampled. If IORDY is inactive then the host shall wait until IORDY is active before the register transfer cycle is completed. If the device is not driving IORDY negated at the tA after the activation of DIORn or DIOWn, then t5 shall be met and tRD is not applicable. If the device is driving IORDY negated at the time tA after the activation of DIORn or DIOWn, then tRD shall be met and t5 is not applicable. (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 31 EP9312 Universal Platform SOC Processor ADDR valid (Note 1) t9 t1 DIORn/ DIOWn t0 WRITE DD(15:0) (Note 2) t2 t2i t3 t4 READ DD(15:0) (Note 2) t5 t6 t6z IORDY (Note 3,3-1) tA IORDY (Note 3,3-2) tC tRD IORDY (Note 3,3-3) tB Note: tC 1. Device address consists of signals CS0n, CS1n and DA (2:0) 2. Data consists of DD (15:0) 3. The negation of IORDY by the device is used to extend the register transfer cycle. The determination of whether the cycle is to be extended is made by the host after tA from the assertion of DIORn or DIOWn. The assertion and negation or IORDY are described in the following three cases: 3-1 Device never negates IORDY, devices keeps IORDY released: no wait is generated. 3-2 Device negates IORDY before tA, but causes IORDY to be asserted before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: no wait generated. 3-3 Device negates IORDY before tA. IORDY is released prior to negation and may be asserted for no more than 5 ns before release: wait generated. The cycle completes after IORDY is reasserted. For cycles where a wait is generated and DIORn is asserted, the device shall place read data on DD (15:0) for tRD before asserting IORDY. Figure 17. PIO Data Transfer to/from Device (c) 32 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Multiword DMA Data Transfer Parameter Cycle time DIORn / DIOWn asserted pulse width DIORn data access DIORn data hold DIORn / DIOWn data setup DIOWn data hold DMACKn to DIORn / DIOWn setup DIORn / DIOWn to DMACKn hold CS (1:0) valid to DIORn / DIOWn CS (1:0) hold DMACKn to read data released (min) (min) (max) (min) (min) (min) (min) (min) (min) (min) (max) (Note) (Note) Symbol t0 tD tE tF tG tH tI tJ tM tN tZ Mode 0 (in ns) Mode 1 (in ns) Mode 2 (in ns) 480 215 150 5 100 20 0 20 50 15 20 150 80 60 5 30 15 0 5 30 10 25 120 70 50 5 20 10 0 5 25 10 25 Note: t0 is the minimum total cycle time, tD is the minimum DIORn / DIOWn assertion time, and tK (tKR or tKW, as appropriate) is the minimum DIORn / DIOWn negation time. A host shall lengthen tD and/or tK to ensure that t0 is equal to the value reported in the devices IDENTIFY DEVICE data. A device implementation shall support any legal host implementation . CSOn/ CS1n DMARQ (Note 1) tM tN tL DMACKn (Note 2) t0 tI DIORn/ DIOWn tE Read DD(15:0) tG Write DD(15:0) tG Note: tJ tD tK tZ tF tH 1. To prevent the transmission of another word of data, the device shall negate DMARQ within the tL specified time once DMACKn is asserted and reassert it again at a later time to resume the DMA operation. Alternatively, if the device is able to continue the transfer of data, the device may leave DMARQ asserted and wait for the host to reassert DMACKn. 2. This signal may be negated by the Host to suspend the DMA transfer in process. 3. This figure shows the transfer of two words. The actual transfer for a given assertion of DMARQ may be any number of words from one to the remaining number of words to be transferred. Figure 18. Multiword DMA Data Transfer (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 33 EP9312 Universal Platform SOC Processor Ultra DMA Data Transfer Figure 19 through Figure 28 define the timings associated with all phases of Ultra DMA bursts. The following table contains the values for the timings for each of the Ultra DMA modes. Timing reference levels = 1.5 V Parameter Symbol Mode 0 (in ns) Mode 1 (in ns) Mode 2 (in ns) Mode 3 (in ns) Mode 4 (in ns) min max min max min max min max min max Typical sustained average two cycle time Cycle time allowing for asymmetry and clock variations (from STROBE edge to STROBE edge) Two cycle time allowing for clock variations (from rising edge to next rising edge or from falling edge to next falling edge of STROBE) Data setup time at recipient Data hold time at recipient Data valid setup time at sender (from data valid until STROBE edge) Data valid hold time at sender (from STROBE edge until data may become invalid) (Note 2) (Note 2) t2CYCTYP 240 tCYC t2CYC tDS tDH tDVS tDVH tFS tLI tMLI tUI tAZ tZAH tZAD tENV 112 230 15 5 70 6 0 0 20 0 20 0 20 230 150 10 70 160 73 154 10 5 48 6 0 0 20 0 20 0 20 200 150 10 70 120 54 115 7 5 30 6 0 0 20 0 20 0 20 170 150 10 70 90 39 86 7 5 20 6 0 0 20 0 20 0 20 130 100 10 55 60 25 57 5 5 6 6 0 0 20 0 20 0 20 120 100 10 55 First STROBE time (for device to first negate DSTROBE from STOP during a data in burst) Limited interlock time Interlock time with minimum Unlimited interlock time Maximum time allowed for output drivers to release (from asserted or negated) Minimum delay time required for output Drivers to assert or negate (from released) Envelope time (from DMACKn to STOP and HDMARDYn during data in burst initiation and from DMACKn to STOP during data out burst initiation) STROBE-to-DMARDYn time (if DMARDYn is negated before this long after STROBE edge, the recipient shall receive no more than one additional data word) Ready-to-final-STROBE time (no STROBE edges shall be sent this long after negation of DMARDYn) Ready-to-pause time (that recipient shall wait to pause after negating DMARDYn) Maximum time before releasing IORDY Minimum time before driving STROBE (Note 4) (Note 3) (Note 3) (Note 3) tSR - 50 - 30 - 20 - NA - NA tRFS tRP tIORDYZ tZIORDY tACK tSS 160 0 20 50 75 20 - 125 0 20 50 70 20 - 100 0 20 50 60 20 - 100 0 20 50 60 20 - 100 0 20 50 60 20 - Setup and hold times for DMACKn (before assertion or negation) Time from STROBE edge to negation of DMARQ or assertion of STOP (when sender terminates a burst) Note: 1. Timing parameters shall be measured at the connector of the sender or receiver to which the parameter applies. 2. The test load for tDVS and tDVH shall be a lumped capacitor load with no cable or receivers. Timing for tDVS and tDVH shall be met for all capacitive loads from 15 to 40 pf where all signals have the same capacitive load value. 3. tUI, tMLI and tLI indicate sender-to-recipient or recipient-to-sender interlocks, i.e., either sender or recipient is waiting for the other to respond with a signal before proceeding. tUI is an unlimited interlock that has no maximum time value. tMLI is a limited time-out that has a defined minimum. tLI is a limited time-out that has a defined maximum. 4. tZIORDY may be greater than tENV since the device has a pull up on IORDYn giving it a known state when released. (c) 34 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor DMARQ (device) DMACKn (host) tUI tFS tACK STOP (host) tACK HDMARDYn (host) tZIORDY DSTROBE (device) tAZ DD (15:0) DA0, DA1, DA2 CS0n, CS1n tACK tDVS tDVH tENV tENV tZAD tZAD Note: The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are not in effect until DMARQ and DMACKn are asserted. Figure 19. Initiating an Ultra DMA data-in Burst (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 35 EP9312 Universal Platform SOC Processor t2CYC tCYC DSTROBE (device) tDVH DD (15:0) (device) DSTROBE (host) tDH DD (15:0) (host) Note: DD (15:0) and DSTROBE signals are shown at both the host and the device to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the host until some time after they are driven by the device. Figure 20. Sustained Ultra DMA data-in Burst tCYC t2CYC tDVS tDVH tDVS tDVH tDS tDH tDS tDH DMARQ (device) DMACKn (host) STOP (host) HDMARDYn (host) DSTROBE (device) DD(15:0) (device) tSR tRFS tRP Figure 21. Host Pausing an Ultra DMA data-in Burst (c) 36 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor DMARQ (device) DMACKn (host) tLI STOP (host) tLI HDMARDYn (host) tSS DSTROBE (device) tZAH tAZ DD (15:0) DA0, DA1, DA2 tACK CS0n, CS1n tDVS CRC tDVH tIORDYZ tACK tLI tMLI tACK Note: The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are no longer in effect after DMARQ and DMACKn are negated. Figure 22. Device Terminating an Ultra DMA data-in Burst (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 37 EP9312 Universal Platform SOC Processor DMARQ (device) tLI DMACKn (host) tZAH tRP STOP (host) tACK HDMARDYn (host) tRFS DSTROBE (device) tDVS DD (15:0) DA0, DA1, DA2 tACK CS0n, CS1n CRC tDVH tLI tMLI tIORDYZ tAZ tACK tMLI Note: The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are no longer in effect after DMARQ and DMACKn are negated. Figure 23. Host Terminating an Ultra DMA data-in Burst (c) 38 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor DMARQ (device) tUI DMACKn (host) tACK STOP (host) tZIORDY DDMARDYn (host) HSTROBE (device) DD (15:0) tDVS DA0, DA1, DA2 tACK CS0n, CS1n tDVH tLI tUI tENV tACK Note: The definitions for the DIOWn:STOP, DIORn:HDMARDYn:HSTROBE and IORDY:DDMARDYn:DSTROBE signal lines are not in effect until DMARQ and DMACKn are asserted. Figure 24. Initiating an Ultra DMA data-out Burst (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 39 EP9312 Universal Platform SOC Processor t2CYC tCYC HSTROBE (host) tDVH DD (15:0) (host) HSTROBE (device) tDH DD (15:0) (device) Note: DD (15:0) and HSTROBE signals are shown at both the device and the host to emphasize that cable settling time as well as cable propagation delay shall not allow the data signals to be considered stable at the device until some time after they are driven by the host. Figure 25. Sustained Ultra DMA data-out Burst tCYC t2CYC tDVS tDVH tDVS tDVH tDS tDH tDS tDH DMARQ (device) tRP DMACKn (host) STOP (host) DDMARDYn (device) HSTROBE (host) DD (15:0) (host) Note: 1. The device may negate DMARQ to request termination of the Ultra DMA burst no sooner than tRP after DDMARDYn is negated. 2. If the tSR timing is not satisfied, the device may receive zero, one, or two more data words from the host. Figure 26. Device Pausing an Ultra DMA data-out Burst tSR tRFS (c) 40 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor DMARQ (device) tLI DMACKn (host) tSS STOP (host) tLI DDMARDYn (device) tACK HSTROBE (host) tDVS DD (15:0) (host) DA0, DA1, DA2 tACK CS0n, CS1n CRC tDVH tIORDYZ tLI tACK tMLI Note: The definitions for the DIOWn:STOP, IORDY:DDMARDYn:DSTROBE and DIORn:HDMARDYn:HSTROBE signal lines are no longer in effect after DMARQ and DMACKn are negated. Figure 27. Host Terminating an Ultra DMA data-out Burst (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 41 EP9312 Universal Platform SOC Processor DMARQ (device) DMACKn (host) tRP STOP (host) tIORDYZ DDMARDYn (device) tRFS HSTROBE (host) tDVS DD (15:0) (host) DA0, DA1, DA2 tACK CS0n, CS1n CRC tDVH tLI tMLI tACK tLI tMLI tACK Note: The definitions for the DIOWn:STOP, IORDY:DDMARDYn:DSTROBE and DIORn:HDMARDYn:HSTROBE signal lines are no longer in effect after DMARQ and DMACKn are negated. Figure 28. Device Terminating an Ultra DMA data-out Burst (c) 42 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Ethernet MAC Interface Min Parameter Symbol 10 Mbit mode 140 140 0 140 140 10 10 400 160 160 10 10 - Typ 10 Mbit mode 400 200 200 10 400 200 200 15 15 - Max 10 Mbit mode 260 260 25 5 260 260 5 5 300 100 Mbit mode 14 14 0 14 14 10 10 400 160 160 10 10 - 100 Mbit mode 40 20 20 10 40 20 20 15 15 - 100 Mbit mode 26 26 25 5 26 26 5 5 300 Unit TXCLK cycle time TXCLK high time TXCLK low time TXCLK to signal transition delay time TXCLK rise/fall time RXCLK cycle time RXCLK high time RXCLK low time RXDVAL / RXERR setup time RXDVAL / RXERR hold time RXCLK rise/fall time MDC cycle time MDC high time MDC low time MDC rise/fall time MDIO setup time (STA sourced) MDIO hold time (STA sourced) MDC to MDIO signal transition delay time (PHY sourced) tTX_per tTX_high tTX_low tTXd tTXrf tRX_per tRX_high tRX_low tRXs tRXh tRXrf tMDC_per tMDC_high tMDC_low tMDCrf tMDIOs tMDIOh tMDIOd ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns STA - Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer (PHY) interface to the wireless medium. PHY - Ethernet physical layer interface. (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 43 EP9312 Universal Platform SOC Processor tTX_high TXCLK MII_TXD[3:0]/ TXEN/ TXERR tTXd tTX_per tTX_low tTXrf tRXrf RXCLK MII_RXD[3:0]/ RXDVAL/ RXERR tRXh tRXs tRX_low tRX_high tRX_per tMDCrf MDC MDIO (Sourced by STA) tMDC_high tMDC_low tMDIOs tMDIOh tMDC_per MDC MDIO (Sourced by PHY) tMDIOd Figure 29. Ethernet MAC Timing Measurement (c) 44 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Audio Interface The following table contains the values for the timings of each of the SPI modes. Parameter SCLK cycle time SCLK high time SCLK low time SCLK rise/fall time Data from master valid delay time Data from master setup time Data from master hold time Data from slave valid delay time Data from slave setup time Data from slave hold time Symbol tclk_per tclk_high tclk_low tclkrf tDMd tDMs tDMh tDSd tDSs tDSh Min - Typ tspix_clk (tspix_clk) / 2 (tspix_clk) / 2 4.5 / 1.5 2 20 40 2 20 40 Max - Unit ns ns ns ns ns ns ns ns ns ns Note: tspix_clk is programmable by the user. (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 45 EP9312 Universal Platform SOC Processor Texas Instruments' Synchronous Serial Format tclk_per tclk_high SCLK tclk_low SFRM SSPTXD/ SSPRXD tclkrf MSB 4 to 16 bits LSB Figure 30. SPI Single Transfer Timing Measurement Microwire tclk_high tclk_per tclkrf SCLK tclk_low SFRM SSPTXD MSB LSB 8-bit control SSPRXD 0 MSB LSB 4 to 16 bits output data Figure 31. Microwire Frame Format, Single Transfer (c) 46 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Motorola SPI tclk_per tclk_high SCLK (SPO=0) tclk_low SCLK (SPO=1) tDMs SSPTXD from master tDMd tDSd SSPRXD from slave SFRM tDSs MSB t DSd LSB MSB t DMh LSB tclkrf Figure 32. SPI Format with SPH=1 Timing Measurement (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 47 EP9312 Universal Platform SOC Processor Inter-IC Sound - I2S Parameter SCLK cycle time SCLK high time SCLK low time SCLK rise/fall time SCLK to LRCLK assert delay time LRCLK from SCLK assert hold time SDI to SCLK deassert setup time SDI from SCLK deassert hold time SCLK to SDO assert delay time SDO from SCLK assert hold time Note: ti2s_clk is programmable by the user. Symbol tclk_per tclk_high tclk_low tclkrf tLRs tLRh tSDIs tSDIh tSDOd tSDOh Min - Typ ti2s_clk (ti2s_clk) / 2 (ti2s_clk) / 2 4 1.5 1.5 20 10 4 4 Max - Unit ns ns ns ns ns ns ns ns ns ns tclk_per tclk_high SCLK tclk_low tclkrf tLRs LRCLK tLRh tSDOs d SDO/SDI tSDOh tSDIs tSDIh Figure 33. Inter-IC Sound (I2S) Timing Measurement (c) 48 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor AC'97 Parameter ABITCLK input cycle time ABITCLK input high time ABITCLK input low time ABITCLK input rise time ABITCLK input fall time ASDI setup to ABITCLK falling ASDI hold after ABITCLK falling ASDI input rise/fall time ABITCLK rising to ASDO / ASYNC valid, C L = 55 pF ASYNC / ASDO rise time, CL = 55 pF ASYNC / ASDO fall time, CL = 55 pF Symbol tclk_per tclk_high tclk_low tclkr tclkf ts th trfin tco trout tfout Min 36 36 2 2 10 10 2 2 2 2 Typ 81.4 23 53 - Max 45 45 6 6 6 15 6 6 Unit ns ns ns ns ns ns ns ns ns ns ns tclk_per ABITCLK tclkrf r tclk_high tclk_low tclkrf f th ts trfin ASDI ASDO tfoutt fout /t rfout tco tco tco ASYNC trout rfout ttfout rfout Figure 34. AC `97 Configuration Timing Measurement (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 49 EP9312 Universal Platform SOC Processor LCD Interface Parameter SPCLK rising time SPCLK falling time SPCLK rising edge to control signal transition time SPCLK rising edge to data transition time SPCLK falling edge to control signal transition time SPCLK falling edge to data transition time Data valid time Symbol tclkr tclkf tCD tDD tCDi tDDi tDv Min - Typ 5 5 1 0 (tSPCLK) / 2 (tSPCLK) / 2 tSPCLK Max - Unit ns ns ns ns ns ns ns tclkr SPCLK HSYNC/ V_CSYNC/ BLANK/ BRIGHT P [17:0] tclkf tCD tDD tDv tclkr SPLCK HSYNC/ V_CSYNC/ BLANK/ BRIGHT P [17:0] tclkf tCDi tDDi tDv Figure 35. LCD Timing Measurement (c) 50 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor ADC Parameter Resolution Integral non-linearity Offset error Full scale error Maximum sample rate Channel switch settling time Noise (RMS) - typical Note: ADIV = 0 ADIV = 1 ADIV = 0 ADIV = 1 Comment No missing codes Range of 0 to 3.3 V Value 50K counts (approximate) 0.01% 15 0.2% 3750 925 500 2 120 Units mV Samples per second Samples per second s ms V ADIV refers to bit 16 in the KeyTchClkDiv register. ADIV = 0 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 4. ADIV = 1 means the input clock to the ADC module is equal to the external 14.7456 MHz clock divided by 16. 61A8 0000 FFFF 9E58 0 Vref/2 Vref A/D Converter Transfer Function (approximately 25,000 counts) Figure 36. ADC Transfer Function Using the ADC: This ADC has a state-machine based conversion engine that automates the conversion process. The initiator for a conversion is the read access of the TSXYResult register by the CPU. The data returned from reading this register contains the result as well as the status bit indicating the state of the ADC. However, this peripheral requires a delay between each successful conversion and the issue of the next conversion command, or else the returned value of successive samples may not reflect the analog input. Since the state of the ADC state machine is returned through the same channel used to initiate the conversion process, there must be a delay inserted after every complete conversion. Note that reading TSXYResult during a conversion will not affect the result of the ongoing process. The following is a recommended procedure for safely polling the ADC from software: 1. Read the TSXYResult register into a local variable to initiate a conversion. 2. If the value of bit 31 of the local variable is '0' then repeat step 1. 3. Delay long enough to meet the maximum sample rate as shown above. 4. Mask the local variable with 0xFFFF to remove extraneous data. 5. If signed mode is used, do a sign extend of the lower halfword. 6. Return the sampled value. (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 51 EP9312 Universal Platform SOC Processor JTAG Parameter TCK clock period TCK clock high time TCK clock low time TMS / TDI to clock rising setup time Clock rising to TMS / TDI hold time JTAG port clock to output JTAG port high impedance to valid output JTAG port valid output to high impedance Symbol tclk_per tclk_high tclk_low tJPs tJPh tJPco tJPzx tJPxz Min 100 50 50 20 45 - Max 30 30 30 Units ns ns ns ns ns ns ns ns TMS TDI tclk_per tclk_high TCK tJPzx TDO tJPco tJPxz tclk_low tJPs tJPh Figure 37. JTAG Timing Measurement (c) 52 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor 352 Pin BGA Package Outline 352-Ball PBGA Diagram O0.30 S C A B O0.10 S C E3 E2 E Ob 3 DETAIL B D3 D2 D (Top View) B A 2 -CA1 -A- e ddd C c E1 -BB D1 O A' A2 DETAIL A' (Bottom View) Figure 38. 352 Pin PBGA Pin Diagram (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 53 EP9312 Universal Platform SOC Processor Table R. 352 Pin Diagram Dimensions dimension in mm Symbol MIN A A1 A2 b c D D1 D2 D3 E E1 E2 E3 e ddd q 2.20 1.12 0.51 26.80 23.80 17.95 26.80 23.80 17.95 - dimension in inches MAX 2.50 1.22 0.61 27.20 24.20 18.05 27.20 24.20 18.05 0.15 NOM 2.30 0.60 1.17 0.75 0.56 27.00 24.13 24.00 18.00 27.00 24.13 24.00 18.00 1.27 30 TYP MIN 0.087 0.044 0.020 1.055 0.937 0.707 1.055 0.937 0.707 - NOM 0.092 0.024 0.046 0.030 0.022 1.063 0.950 0.945 0.709 1.063 0.950 0.945 0.709 0.050 30 TYP MAX 0.098 0.048 0.024 1.071 0.953 0.711 1.071 0.953 0.711 0.006 Note: 1. Controlling Dimension: Millimeter. 2. Primary Datum C and seating plane are defined by the spherical crowns of the solder balls. 3. Dimension b is measured at the maximum solder ball diameter, parallel to Primary Datum C. 4. There shall be a minimum clearance of 0.25 mm between the edge of the solder ball and the body edge. 5. Reference Document: JEDEC MO-151, BAL-2 352 Pin BGA Pinout (Bottom View) The following table shows the 352 pin BGA pinout. (For better understanding, compare the coordinates on the x and y axis on Figure 40, "352 PIN BGA PINOUT", on page 55 with Figure 38, "352 Pin PBGA Pin Diagram", on page 53. * VDD_core is CVDD. * VDD_ring is RVDD. * All core and ring grounds are connected together and are labelled GND. * Other special power requirements are clearly labelled (i.e. H18=ADC_VDD and H19=ADC_GND). * NC means that the pin is not connected. (c) 54 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 (c) 55 1 Y HSYNC W V U T R P 2 3 4 5 6 7 8 9 EP9312 Universal Platform SOC Processor Figure 40. 352 PIN BGA PINOUT 10 11 12 13 14 15 16 17 18 19 20 DD[1] P[9] P[11] P[15] BLANK DD[12] DD[0] P[8] P[10] P[13] P[2] P[5] DD[15] P[7] SPCLK AD[15] DA[6] P[3] DD[13] P[6] DA[7] P[1] P[4] P[12] P[16] AD[0] DA[8] AD[2] AD[4] N DA[13] M AD[7] L DA[18] K AD[22] J H G F V_CSY DD[1 NC 4] RVD AD[1] P[17] P[14] RVDD D RVD DA[10] DA[9] BRIGHT RVDD D CVD DA[12] DA[11] AD[3] CVDD D DA[14] AD[6] AD[5] CVDD GND RVDD AD[10 DA[4] ] AD[11 DA[5] ] AD[1 AD[12 4] ] AD[13 P[0] ] CVD GND D CVD GND D IDEDA[ DA[1] AD[8] 0] IDECS1 IDEDA[ AD[9] N 1] IDECS0 IDEDA[ DA[2] N 2] DA[3] RVDD DA[0] GND DTRN TCK TDI TDO TMS GND NC CVDD CVDD BOOT[0] EEDAT EECLK ASDO SFRM1 INT[3] RTSN RDLED USBP[1] ABITCLK Y SLA[1] USBP[0] SLA[0] CTSN RXD[2] W TXD[0] V SCLK1 GRLED ASYNC SSPTX1 INT[2] SSPRX1 GND GND INT[1] DSRN BOOT[1] GND RVDD PWMO USBM[0] RXD[1] TXD[1] UT USBM[1 RXD[0] TXD[2] ROW[2] INT[0] ] PLL_GN RVDD RVDD ROW[0] ROW[3] D PLL_VD ROW[6] RVDD RVDD XTALI D GND GND GND CVDD CVDD XTALO COL[4] COL[5] SYM COL[0] COL[3] COL[1] COL[6] ROW[1] U ROW[4] T ROW[5] R ROW[7] P COL[2] N Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND CSN[0] M PRSTN SXP YM L K J DA[17] DA[16] DA[15] DA[20] AD[21] DA[19] COL[7] RSTON SYP SXM YP DQMN[ DQMN[ DA[21] 0] 1] DQMN[ CASN RASN 3] SDCSN[ SDCSN[ SDWE 0] 1] N SDCSN[ DA[22] DA[24] 3] DQMN[2 GND ] SDCSN[ CVDD 2] SDCLK AD[25] RVDD RVD D RVDD CVDD GND GND RVDD CVDD NC NC NC CLD 13 RVDD GND GND AD[19] DD[10] DD[7] DD[4] 5 E AD[23] D AD[24] DA[23] DA[26] CSN[6] DA[25] DD[11] SDCLK EN C CSN[1] CSN[3] AD[20] DA[29] B CSN[2] DA[31] DA[30] DA[27] A CSN[7] DA[28] AD[18] 1 2 3 DD[8] 4 CVD D CVD CVD RVDD GND D D AD[16 MIIRXD[ DD[9] DD[5] ] 2] MIIRXD[ DD[6] DD[2] MDC 3] MIIRXD[ DD[3] WRN MDIO 1] RXCL MIIRXD[ AD[1 RDN K 0] 7] 6 7 8 9 GND GND EGPIO[ 14] NC NC NC 15 CVDD NC NC NC NC 14 RTCXTA XM CVDD LI RTCXTA ADC_V RVDD LO DD EGPIO[ RVDD EGPIO[7] 9] EGPIO[ GND EGPIO[2] 4] EGPIO[ ASDI DIOWN 0] NC NC NC NC 16 ADC_G XP H ND EGPIO[1 EGPIO[11 G 0] ] EGPIO[6 EGPIO[8] F ] EGPIO[3 EGPIO[5] E ] MIITXD[ TXEN NC 3] MIITXD[ NC TXCLK 0] MIITXD[ CRS RXERR 1] RXDVA MIITXD[ TXERR L 2] 10 11 12 USBM[2] ARSTN DIORN EGPIO[1] D NC USBP[2] IORDY DMACKN C TRSTN B NC 20 A EGPIO[1 NC WAITN 3] EGPIO[1 EGPIO[ NC 2] 15] 17 18 19 EP9312 Universal Platform SOC Processor Pin List The following Plastic Ball Grid Array (PBGA) ball assignment table is sorted in order of ball. Ball A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C1 C2 Signal CSN[7] DA[28] AD[18] DD[8] DD[4] AD[17] RDN RXCLK MIIRXD[0] RXDVAL MIITXD[2] TXERR CLD NC NC NC EGPIO[12] EGPIO[15] NC NC CSN[2] DA[31] DA[30] DA[27] DD[7] DD[3] WRN MDIO MIIRXD[1] RXERR MIITXD[1] CRS NC NC NC NC EGPIO[13] NC WAITN TRSTN CSN[1] CSN[3] Ball E9 E10 E11 E12 E13 E14 E15 E16 E17 E18 E19 E20 F1 F2 F3 F4 F5 F6 F7 F14 F15 F16 F17 F18 F19 F20 G1 G2 G3 G4 G5 G6 G15 G16 G17 G18 G19 G20 H1 H2 H3 H4 Signal RVDD GND GND RVDD CVDD CVDD GND ASDI DIOWN EGPIO[0] EGPIO[3] EGPIO[5] SDCSN[3] DA[22] DA[24] AD[25] RVDD GND CVDD CVDD GND GND EGPIO[2] EGPIO[4] EGPIO[6] EGPIO[8] SDCSN[0] SDCSN[1] SDWEN SDCLK RVDD RVDD RVDD RVDD EGPIO[7] EGPIO[9] EGPIO[10] EGPIO[11] DQMN[3] CASN RASN SDCSN[2] Ball L3 L4 L5 L8 L9 L10 L11 L12 L13 L16 L17 L18 L19 L20 M1 M2 M3 M4 M5 M8 M9 M10 M11 M12 M13 M16 M17 M18 M19 M20 N1 N2 N3 N4 N5 N6 N8 N9 N10 N11 N12 N13 Signal DA[16] DA[15] GND GND GND GND GND GND GND CVDD COL[5] COL[7] RSTON PRSTN AD[7] DA[14] AD[6] AD[5] CVDD GND GND GND GND GND GND GND COL[4] COL[3] COL[6] CSN[0] DA[13] DA[12] DA[11] AD[3] CVDD CVDD GND GND GND GND GND GND Ball T13 T14 T15 T16 T17 T18 T19 T20 U1 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V1 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11 V12 V13 V14 Signal CVDD GND INT[0] USBM[1] RXD[0] TXD[2] ROW[2] ROW[4] AD[0] P[15] P[10] P[7] P[6] P[4] P[0] AD[13] DA[3] DA[0] DSRN BOOT[1] NC SSPRX1 INT[1] PWMOUT USBM[0] RXD[1] TXD[1] ROW[1] P[16] P[11] P[8] DD[15] DD[13] P[1] AD[14] AD[12] DA[2] IDECS0N IDEDA[2] TDI GND ASYNC (c) 56 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Ball C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E1 E2 E3 E4 E5 E6 E7 E8 Signal AD[20] DA[29] DD[10] DD[6] DD[2] MDC MIIRXD[3] TXCLK MIITXD[0] NC NC NC NC NC NC USBP[2] IORDY DMACKN AD[24] DA[25] DD[11] SDCLKEN AD[19] DD[9] DD[5] AD[16] MIIRXD[2] MIITXD[3] TXEN NC NC NC EGPIO[14] NC USBM[2] ARSTN DIORN EGPIO[1] AD[23] DA[23] DA[26] CSN[6] GND GND CVDD CVDD Ball H5 H8 H9 H10 H11 H12 H13 H16 H17 H18 H19 H20 J1 J2 J3 J4 J5 J8 J9 J10 J11 J12 J13 J16 J17 J18 J19 J20 K1 K2 K3 K4 K5 K8 K9 K10 K11 K12 K13 K16 K17 K18 K19 K20 L1 L2 Signal CVDD GND GND GND GND GND GND RVDD RTCXTALO ADC_VDD ADC_GND XP DA[21] DQMN[0] DQMN[1] DQMN[2] GND GND GND GND GND GND GND CVDD RTCXTALI XM YP YM AD[22] DA[20] AD[21] DA[19] RVDD GND GND GND GND GND GND CVDD SYM SYP SXM SXP DA[18] DA[17] Ball N15 N16 N17 N18 N19 N20 P1 P2 P3 P4 P5 P6 P15 P16 P17 P18 P19 P20 R1 R2 R3 R4 R5 R6 R7 R8 R13 R14 R15 R16 R17 R18 R19 R20 T1 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 Signal GND GND XTALO COL[0] COL[1] COL[2] AD[4] DA[10] DA[9] BRIGHT RVDD RVDD RVDD RVDD XTALI PLL_VDD ROW[6] ROW[7] AD[2] AD[1] P[17] P[14] RVDD RVDD GND CVDD CVDD GND RVDD RVDD ROW[0] ROW[3] PLL_GND ROW[5] DA[8] BLANK P[13] SPCLK V_CSYNC DD[14] GND CVDD RVDD GND GND RVDD Ball V15 V16 V17 V18 V19 V20 W1 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal SSPTX1 INT[2] RTSN USBP[0] CTSN TXD[0] P[12] P[9] DD[0] P[5] P[3] DA[7] DA[5] AD[11] AD[9] IDECS1N IDEDA[1] TCK TMS EECLK SCLK1 GRLED INT[3] SLA[1] SLA[0] RXD[2] HSYNC DD[1] DD[12] P[2] AD[15] DA[6] DA[4] AD[10] DA[1] AD[8] IDEDA[0] DTRN TDO BOOT[0] EEDAT ASDO SFRM1 RDLED USBP[1] ABITCLK (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 57 EP9312 Universal Platform SOC Processor The following section focuses on the EP9312 pin signals from two viewpoints - the pin usage and pad characteristics, and the pin multiplexing usage. The first table (Table S) is a summary of all the EP9312 pin signals. The second table (Table T) illustrates the pin signal multiplexing and configuration options. Table S is a summary of the EP9312 pin signals, which illustrates the pad type and pad pull type (if any). The symbols used in the table are defined as follows. (Note: A blank box means Not Applicable (NA) or, for Pull Type, No Pull (NP).) Under the Pad Type column: * A - Analog pad * P - Power pad * G - Ground pad * I - Pin is an input only * I/O - Pin is input/output * 4mA - Pin is a 4 mA output driver * 8mA - Pin is an 8 mA output driver * 12mA - Pin is an 12 mA output driver See the text description for additional information about bi-directional pins. Under the Pull Type Column: * * PU - Resistor is a pull up to the RVDD supply PD - Resistor is a pull down to the RGND supply . Table S. Pin Descriptions Pin Name TCK TDI TDO TMS TRSTn BOOT[1:0] XTALI XTALO VDD_PLL GND_PLL RTCXTALI RTCXTALO WRn RDn WAITn AD[25:0] DA[31:0] CSn[3:0] CSn[7:6] DQMn[3:0] SDCLK SDCLKEN SDCSn[3:0] RASn CASn SDWEn P[17:0] SPCLK HSYNC Block JTAG JTAG JTAG JTAG JTAG System PLL PLL PLL PLL RTC RTC PBUS PBUS PBUS PBUS PBUS PBUS PBUS PBUS SDRAM SDRAM SDRAM SDRAM SDRAM SDRAM Raster Raster Raster Pad Type I I 4ma I I I A A P G A A 4ma 4ma I 8ma 8ma 4ma 4ma 8ma 8ma 8ma 4ma 8ma 8ma 8ma 4ma 12ma 8ma PU PU PU PU PU PU PU PD PD PD Pull Type PD PD JTAG clock in JTAG data in JTAG data out JTAG test mode select JTAG reset Boot mode select in Main oscillator input Main oscillator output Main oscillator power, 1.8V Main oscillator ground RTC oscillator input RTC oscillator output SRAM Write strobe out SRAM Read / OE strobe out SRAM Wait in Shared Address bus out Shared Data bus in/out Chip select out Chip select out Shared data mask out SDRAM clock out SDRAM clock enable out SDRAM chip selects out SDRAM RAS out SDRAM CAS out SDRAM write enable out Pixel data bus out Pixel clock in/out Horizontal synchronization / line pulse out Pin Name Description V_CSYNC BLANK BRIGHT PWMOUT Xp, Xm Yp, Ym sXp, sXm sYp, sYm VDD_ADC GND_ADC COL[7:0] ROW[7:0] USBp[2:0] USBm[2:0] TXD0 RXD0 CTSn DSRn DTRn RTSn TXD1 RXD1 TXD2 RXD2 MDC MDIO RXCLK MIIRXD[3:0] RXDVAL Table S. Pin Descriptions (Continued) Block Pad Type 8ma 8ma 4ma 8ma A A A A P G 8ma 8ma A A 4ma I I I 4ma 4ma 4ma I 4ma I 4ma 4ma I I I PU PD PD PD PU PU PU PU PU PU PU Pull Type PU PU Description Vertical or composite synchronization / frame pulse out Composite blanking signal out PWM brightness control out Pulse width modulator output Touchscreen ADC X axis Touchscreen ADC Y axis Touchscreen ADC X axis feedback Touchscreen ADC Y axis feedback Touchscreen ADC power, 3.3V Touchscreen ADC ground Key matrix column inputs Key matrix row outputs USB positive signals USB negative signals Transmit out Receive in Clear to send / transmit enable Data set ready / Data Carrier Detect Data Terminal Ready output Ready to send Transmit / IrDA output Receive / IrDA input Transmit Receive Management data clock Management data input/output Receive clock in Receive data in Receive data valid Raster Raster Raster PWM ADC ADC ADC ADC ADC ADC Key Key USB USB UART1 UART1 UART1 UART1 UART1 UART1 UART2 UART2 UART3 UART3 EMAC EMAC EMAC EMAC EMAC (c) 58 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Table S. Pin Descriptions (Continued) Pin Name RXERR TXCLK MIITXD[3:0] TXEN TXERR CRS CLD GRLED RDLED EECLK EEDAT ABITCLK ASYNC ASDI ASDO ARSTn SCLK1 SFRM1 SSPRX1 SSPTX1 INT[3:0] PRSTn RSTOn SLA[1:0] EGPIO[15:0] DD[15:0] IDEDA[2:0] IDECS0n IDECS1n DIORn DIOWn DMACKn IORDY CVDD RVDD CGND RGND Block EMAC EMAC EMAC EMAC EMAC EMAC EMAC LED LED EEPROM EEPROM AC97 AC97 AC97 AC97 AC97 SPI1 SPI1 SPI1 SPI1 INT Syscon Syscon EEPROM GPIO IDE IDE IDE IDE IDE IDE IDE IDE Power Power Ground Ground Pad Type I 4ma I 4ma 4ma I I 12ma 12ma 4ma 4ma 8ma 8ma I 8ma 8ma 8ma 8ma I 8ma I I 4ma 4ma I/O, 4ma 8ma 8ma 8ma 8ma 8ma 8ma 8ma I P P G G PU PU PU PD PU PD PD PD PU PU PD PD PD PU Pull Type PD PU PD PD PD PD PU Description Receive data error Transmit clock in Transmit data out Transmit enable Transmit error Carrier sense Collision detect Green LED Red LED EEPROM / Two-wire Interface clock EEPROM / Two-wire Interface data AC97 bit clock AC97 frame sync AC97 Primary input AC97 output AC97 reset SPI bit clock SPI Frame Clock SPI input SPI output External interrupts Power on reset User Reset in out - open drain Flash programming voltage control Enhanced GPIO IDE data bus IDE Device address output IDE Chip Select 0 output IDE Chip Select 1 output IDE Read strobe output IDE Write strobe output IDE DMA acknowledge output IDE ready input Digital power, 1.8V Digital power, 3.3V Digital ground Digital ground (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 59 EP9312 Universal Platform SOC Processor Table T illustrates the pin signal multiplexing and configuration options. Table T. Pin Multiplex Usage Information Physical Pin Name COL[7:0] ROW[7:0] EGPIO[0] EGPIO[1] EGPIO[2] EGPIO[3] EGPIO[4] EGPIO[5] EGPIO[6] EGPIO[7] EGPIO[8] EGPIO[9] EGPIO[10] EGPIO[11] EGPIO[12] EGPIO[13] EGPIO[14] EGPIO[15] ABITCLK ASYNC ASDO ASDI ARSTn SCLK1 SFRM1 SSPTX1 SSPRX1 IDEDA[2:0] IDECS0n IDECS1n DIORn DD[7:0] DD[15:12] Description GPIO GPIO Ring Indicator Input 1Hz clock monitor IDE DMA request Transmit Enable output / HDLC clocks I2S Transmit Data 1 I2S Receive Data 1 I2S Transmit Data 2 DMA Request 0 DMA Acknowledge 0 DMA EOT 0 DMA Request 1 DMA Acknowledge 1 DMA EOT 1 I2S Receive Data 2 PWM 1 output IDE Device active / present I2S Serial clock I2S Frame Clock I2S Transmit Data 0 I2S Receive Data 0 I2S Master clock I2S Serial clock I2S Frame Clock I2S Transmit Data 0 I2S Receive Data 0 GPIO GPIO GPIO GPIO GPIO GPIO Multiplex signal name GPIO Port D[7:0] GPIO Port C[7:0] RI CLK1HZ DMARQ TENn / HDLCCLK1 / HDLCCLK3 SDO1 SDI1 SDO2 DREQ0 DACK0 DEOT0 DREQ1 DACK1 DEOT1 SDI2 PWMOUT1 DASP SCLK LRCK SDO0 SDI0 MCLK SCLK LRCK SDO0 SDI0 GPIO Port E[7:5] GPIO Port E[4] GPIO Port E[3] GPIO Port E[2] GPIO Port H[7:0] GPIO Port G[7:4] (c) 60 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 EP9312 Universal Platform SOC Processor Acronyms and Abbreviations The following tables list abbreviations and acronyms used in this data sheet. Term ADC ALT AMBA ATAPI CODEC CRC DAC DMA Term PHY PIO Definition Ethernet PHYsical layer interface Programmed I/O Reduced Instruction Set Computer Secure Digital Music Initiative Synchronous Dynamic RAM Serial Peripheral Interface Static Random Access Memory Station - Any device that contains an IEEE 802.11 conforming Medium Access Control (MAC) and physical layer (PHY) interface to the wireless medium Thin Film Transistor Translation Lookaside Buffer Universal Serial Bus Definition RISC Analog-to-Digital Converter SDMI Alternative SDRAM Advanced Micro-controller Bus Architecture SPI ATA Packet Interface SRAM COder / DECoder Cyclic Redundancy Check Digital-to-Analog Converter TFT Direct-Memory Access TLB STA EEPROM Electronically Erasable Programmable Read Only Memory USB EMAC FIFO FIQ FLASH GPIO HDLC I/F I 2S IC ICE IDE IEEE IrDA IRQ ISO JTAG LFSR MII MMU OHCI Ethernet Media Access Controller First In / First Out Fast Interrupt Request Flash memory General Purpose I/O High-level Data Link Control Interface Inter-IC Sound Integrated Circuit In-Circuit Emulator Integrated Drive Electronics Institute of Electronics and Electrical Engineers Infrared Data Association Standard Interrupt Request International Standards Organization Joint Test Action Group Linear Feedback Shift Register Media Independent Interface Memory Management Unit Open Host Controller Interface Units of Measurement Symbol Unit of Measure degree Celsius Hertz = cycle per second Kilobits per second Kilobyte KiloHertz = 1000 Hz Megabits per second MegaHertz = 1,000 KiloHertz microAmpere = 10-6 Ampere microsecond = 1,000 nanoseconds = 10-6 seconds milliAmpere = 10-3 Ampere millisecond = 1,000 microseconds = 10-3 seconds milliWatt = 10-3 Watts nanosecond = 10-9 seconds picoFarad = 10-12 Farads Volt Watt C Hz Kbps Kbyte KHz Mbps MHz A s mA ms mW ns pF V W (c) DS515PP6 Copyright 2004 Cirrus Logic (All Rights Reserved) 61 EP9312 Universal Platform SOC Processor ORDERING INFORMATION The order numbers for the device are: EP9312-CB EP9312-CBZ EP9312-IB EP9312-IBZ 0C to +70C 0C to +70C -40C to +85C -40C to +85C 352-pin PBGA 352-pin PBGA 352-pin PBGA 352-pin PBGA Lead Free Lead Free EP9312 -- CBZ Lead Material: Z = Lead Free Part Number Product Line: Embedded Processor Package Type: B = 352-Ball, Plastic Ball Grid Array (27 mm x 27 mm) Temperature Range: C = Commercial E = Extended Operating Version I = Industrial Operating Version Note: Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative. Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find one nearest you go to www.cirrus.com IMPORTANT NOTICE "Preliminary" product information describes products that are in production, but for which full characterization data is not yet available. Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS (INCLUDING MEDICAL DEVICES, AIRCRAFT SYSTEMS OR COMPONENTS AND PERSONAL OR AUTOMOTIVE SAFETY OR SECURITY DEVICES). INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, MaverickCrunch, MaverickKey, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Microsoft and Windows are registered trademarks of Microsoft Corporation. Microwire is a trademark of National Semiconductor Corp. National Semiconductor is a registered trademark of National Semiconductor Corp. Texas Instruments is a registered trademark of Texas Instruments, Inc. Motorola is a registered trademark of Motorola, Inc. LINUX is a registered trademark of Linus Torvalds. (c) 62 Copyright 2004 Cirrus Logic (All Rights Reserved) DS515PP6 |
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